Small Outline Transistor Normally specified without dash between SOT and the number:
The number after the dash is the number of pins.
The EIAJ SOIC body was supposed to be approximately 5.3 mm wide, while the JEDEC SOIC body was supposed to be approximately 3.8 mm leading to endless confusion.
Despite what you will read, there is not one standard - every company was smoking something different and the designations were used for what the engineer thought it meant rather than what it might have meant, thus it is important to use the pitch, pin-count, and body-width in the foot-print name. SOIC or SO or SOP or SOG etc etc.. do not have precise meanings! You have been warned. It is not a good idea to assume that one SOP-8 is the same as another - always look at the data sheets! As a default use the SO designation.
While the names differ a bit, all of these can be specified with just a few numbers:
Thus SO(LP)-(PC)-(BW) is all we normally need. One can add a LT at the end if needed.
Normal lead pitch is 1.27mm - most common best designated as
Less common would be the wide one Best designated as
Sometime called SOIC-8W or SO-8W
SOIC are supposed to fall into standard body-widths - but of course there are exceptions.
If you look at manufactures recommended land-patterns(foot-prints) for the same package you will find variation. There can be variations based on trade-offs of placement density vs reliability.
optoisolators can have 2.54mm pitch Example SO254-4-4.4 - 2.54mm pitch, 4 pins, 4.4mm body width, but the pins are narrow like a 127 pitch.
SO(SOP) with pin spacings less than 1.27 mm include PSOP, TSOP,TSSOP
Thin small outline package (TSOP)
Thin-shrink small outline package (TSSOP)
Shrink small outline package (SSOP)
Best called micro-SOIC. This case is much smaller with a pitch of only 0.5mm - always check the data sheet! MSOIC50-10-3.0 case 0.5mm pitch - 10 pins - 3mm width
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